? 2004 california micro devices corp. all rights reserved. 02/02/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 1 CM1208-07/08 7 & 8-channel high-speed esd protection arrays features ? seven or eight channels of high-speed esd pro- tection meets iec-61000-4-2 level 4 esd protection requirements (+ 8kv contact discharge) meets iec-61000-4-2 + 15kv air discharge requirements low loading capacitance at 3pf typical low supply and leakage currents ? ideal for bat- tery-powered devices small msop-10 package lead-free versions available applications high speed data line esd protection dvi ports high resolution video (e.g. vga ports) expansion ports for notebook/handheld computers 5v pseudo rs-232 ports product description the CM1208-07/CM1208-08 is a diode array designed to provide either 7 or 8 channels of esd protection for electronic components or sub-systems. each channel consists of a pair of diodes, which steers the esd cur- rent pulse to either the positive (v p ) or negative (v n ) supply. the CM1208-07/08 devices will protect against esd pulses up to 15kv contact discharge per the inter- national standard iec61000-4-2. these devices are particularly well-suited for portable electronics (e.g.handheld and notebook computers) because of its small package footprint, high esd pro- tection level, and low loading capacitance. they are also suitable for protecting video output lines and i/o ports in computers, set top boxes, digital tvs and peripheral equipment. the CM1208-07/CM1208-08 is housed in a 10 pin msop package and is available with optional lead-free finishing. electrical schematics ch3 v n ch6 ch4 ch5 ch1 v p CM1208-07 v n ch2 ch7 ch3 v n ch6 ch4 ch5 ch1 v p CM1208-08 ch8 ch2 ch7
? 2004 california micro devices corp. all rights reserved. 2 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 02/02/04 CM1208-07/08 ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. pin descriptions device pin name type description -07,-08 1 ch 1 i/o esd channel -07,-08 2 ch 2 i/o esd channel -07,-08 3 ch 3 i/o esd channel -07,-08 4 ch 4 i/o esd channel -07,-08 5 v n gnd negative voltage supply rail or ground reference rail -07,-08 6 ch 5 i/o esd channel -07,-08 7 ch 6 i/o esd channel -07,-08 8 v p supply positive voltage supply rail -07,-08 9 ch 7 i/o esd channel -07 10 v n gnd negative voltage supply rail or ground reference rail -08 10 ch 8 i/o esd channel package / pinout diagrams note: these drawings are not to scale. 10-pin msop 1 2 3 4 10 9 8 7 ch1 ch2 ch3 ch4 v n ch7 v p ch6 top view 56 v n ch5 10-pin msop 1 2 3 4 10 9 8 7 ch1 ch2 ch3 ch4 ch8 ch7 v p ch6 top view 56 v n ch5 CM1208-08ms CM1208-07ms CM1208-08mr CM1208-07mr part numbering information pins package standard finish lead-free finish ordering part number 1 part marking ordering part number 1 part marking 10 msop CM1208-07ms 0807 CM1208-07mr 807r 10 msop CM1208-08ms 0808 CM1208-08mr 808r
? 2004 california micro devices corp. all rights reserved. 02/02/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 3 CM1208-07/08 specifications note 1: only one diode conducting at a time. absolute maximum ratings parameter rating units supply voltage (v p - v n )6.0v diode forward dc current (note 1) 20 ma operating temperature range -40 to +85 c storage temperature range -65 to +150 c dc voltage at any channel input (v n - 0.5) to (v p + 0.5) v package power rating msop package 300 mw standard operating conditions parameter rating units operating temperature range -40 to +85 c operating supply voltage (v p - v n ) 0 to 5.5 v
? 2004 california micro devices corp. all rights reserved. 4 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 02/02/04 CM1208-07/08 note 1: all parameters specified at t a =-40 to +85c unless otherwise noted. note 2: these parameters guaranteed by design and characterization. note 3: from i/o pins to v p or v n only. a bypass capacitor between v p and v n is required. it is recommended that v p be bypassed to v n with a 0.2 f ceramic capacitor. note 4: human body model per mil-std-883, method 3015, c discharge = 100pf, r discharge = 1.5k ?, v p = 5.0v, v n grounded. note 5: standard iec 61000-4-2 with c discharge = 150pf, r discharge = 330 ? , v p = 5.0v, v n grounded. performance information typical channel input capacitance vs. channel input voltage at t a =25c electrical operating characteristics (see note 1) symbol parameter conditions min typ max units i p supply current (v p -v n )=5.0v 10 a v f diode forward voltage top diode bottom diode i f = 20ma; t a =25c 0.60 0.65 0.7 0.8 0.95 0.95 v v i leak channel leakage current t a =25c 0.1 1.0 a c in channel input capacitance at 1 mhz, osc level = 30mv, v p =5v, v n =0v, v ch =2.5v; note 2 applies 35pf v esd esd protection peak discharge voltage at any chan- nel input a) contact discharge per iec 61000-4-2 standard b) human body model, mil- std-883, method 3015 notes 2, 3 & 5 notes 2, 3 & 4 8 15 kv kv v cl channel clamp voltage positive transients negative transients at 8kv esd hbm; t a =25c; note 2, 3 & 4 v p + 5.0 v n - 5.0 v v typical variation of c in vs. v in (v p = 5v, v n = 0v, 0.2 f chip capacitor between v p and v n ) 0 1 2 3 4 5 012345 input voltage input capacitance (p f)
? 2004 california micro devices corp. all rights reserved. 02/02/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 5 CM1208-07/08 application information design considerations in order to realize the maximum protection against esd pulses, care must be taken in the pcb layout to minimize parasitic series inductances on the supply/ ground rails as well as the signal trace segment between the signal input (typically a connector) and the esd protection device. refer to figure 1 , which illus- trates an example of a positive esd pulse striking an input channel. the parasitic series inductance back to the power supply is represented by l 1 and l 2 . the volt- age v cl on the line being protected is: v cl = fwd voltage drop of d 1 + v supply + l 1 x d(i esd ) / dt + l 2 x d(i esd ) / dt where i esd is the esd current pulse, and v supply is the positive supply voltage. an esd current pulse can rise from zero to its peak value in a very short time. as an example, a level 4 contact discharge per the iec61000-4-2 standard results in a current pulse that rises from zero to 30 amps in 1ns. here d(i esd )/dt can be approximated by ? i esd / ? t, or 30/(1x10 -9 ). so just 10nh of series induc- tance (l 1 and l 2 combined) will lead to a 300v incre- ment in v cl ! similarly for negative esd pulses, parasitic series inductance from the v n pin to the ground rail will lead to drastically increased negative voltage on the line being protected. another consideration is the output impedance of the power supply for fast transient currents. most power supplies exhibit a much higher output impedance to fast transient current spikes. in the v cl equation above, the v supply term, in reality, is given by (v dc + i esd x r out ), where v dc and r out are the nominal supply dc output voltage and effective output imped- ance of the power supply respectively. as an example, a r out of 1 ohm would result in a 10v increment in v cl for a peak i esd of 10a. to mitigate these effects, a high frequency bypass capacitor should be connected between the v p pin of the esd protection array and the ground plane. the value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the esd pulse with minimal change in v p . typically a value in the 0.1f to 0.2f range is adequate for iec-61000-4- 2 level 4 contact discharge protection (8kv). for higher esd voltages, the bypass capacitor should be increased accordingly. ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. electrolytic capaci- tors should be avoided as they have poor high fre- quency characteristics. for extra protection, connect a zener diode in parallel with the bypass capacitor to mit- igate the effects of the parasitic series inductance inherent in the capacitor. the breakdown voltage of the zener diode should be slightly higher than the maxi- mum supply voltage. as a general rule, the esd protection array should be located as close as possible to the point of entry of expected electrostatic discharges. the power supply bypass capacitor mentioned above should be as close to the v p pin of the protection array as possible, with minimum pcb trace lengths to the power supply, ground planes and between the signal input and the esd device to minimize stray series inductance. additional information see also california micro devices application note ap209, ?design considerations for esd protection.? figure 1. application of positive esd pulse between input channel and ground n l 2 l 1 v p v path of esd current pulse i one channel of CM1208 channel input ground rail chassis ground positive supply rail system or circuitry being protected line being protected esd d 1 2 d 0a 20a v cl
? 2004 california micro devices corp. all rights reserved. 6 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 02/02/04 CM1208-07/08 mechanical details msop mechanical specifications: CM1208-07/08 devices are packaged in 10-pin msop packages. dimensions are presented below. for complete information on the msop-10 package, see the california micro devices msop package infor- mation document. * this is an approximate number which may vary. package dimensions for msop-10 package dimensions package msop pins 10 dimensions millimeters inches min max min max a 0.75 0.95 0.028 0.038 a1 0.05 0.15 0.002 0.006 b 0.18 0.40 0.006 0.016 c 0.18 0.007 d 2.90 3.10 0.114 0.122 e 2.90 3.10 0.114 0.122 e 0.50 bsc 0.0196 bsc h 4.76 5.00 0.187 0.197 l 0.40 0.70 0.0137 0.029 # per tube 80 pieces* # per tape and reel 4000 controlling dimension: inches mechanical package diagrams e d h 1234 10 9 8 7 l end view c e b a a1 seating plane side view top view 6 5 pin 1 marking
|
